What are the breakdowns of MOSFETs?
Source, Drain, Gate
Three-pole of FET: source level S drain level D gate level G
(I don't talk about the gate GOX breakdown here, only for the drain voltage breakdown)
First, the test conditions are that the source gate substrate is grounded, and then the drain voltage is scanned until the Drain terminal current reaches 1uA. So from the device structure, there are three leakage channels: Drain to source, Drain to Bulk, Drain to Gate.
1) Drain-"Source punch through:
This is mainly caused by Drain plus reverse bias voltage, which makes the Drain/Bulk PN junction depletion region extend. When the depletion region hits the Source, the source and drain do not need to be turned on to form a path, so it is called punch-through ( Punch through). How to prevent punch-through? This is going back to the reverse bias characteristic of the diode. The width of the depletion region is related to the voltage and the doping concentration on both sides. The higher the concentration, the more the extension of the depletion region can be suppressed. Therefore, there is an anti-punch-through injection in the flow (APT). : AnTI Punch Through), remember that it is going to hit the specis of the same type as well. Of course, the BV that actually encountered WAT ran and decided to go from the Source side. It may be necessary to see if PolyCD or Spacer width, or LDD_IMP problem, how to eliminate it? It depends on whether you ran NMOS and PMOS. The POLY CD can be verified by the Poly related WAT. Right?
For punch-through breakdown, there are some features:
(1) The breakdown point of the punch-through breakdown is soft. During the breakdown process, the current has a gradually increasing characteristic. This is because the depletion layer expands wider and generates a larger current. On the other hand, the widening of the depletion layer is prone to the DIBL effect, and the source substrate is positively biased to exhibit a gradual increase in current.
(2) The soft breakdown point of the punch-through breakdown occurs when the depletion layer of the source and drain contacts, and the carrier at the source is injected into the depletion layer.
The electric field in the depleted layer is accelerated to reach the drain end. Therefore, the current through the breakdown also has a sharp increase point. The sharp increase of this current is different from the sharp increase in the avalanche breakdown. The current at this time is equivalent to the source substrate. The current of the PN junction is guided by the current, and the current when the avalanche is broken is mainly the avalanche current when the PN junction is reversely broken. If no current is limited, the current of the avalanche breakdown is large.
(3) Punch through breakdown generally does not cause destructive breakdown. Because the punch-through field strength does not reach the field strength of avalanche breakdown, a large number of electron-hole pairs are not generated.
(4) Punch-through breakdown generally occurs in the channel body, and the channel surface is not prone to punch-through. This is mainly due to the fact that the channel concentration causes the surface concentration to be larger than the concentration. Therefore, the NMOS tube generally has anti-punch-through injection.
(5) In general, the concentration of the edge of the beak is greater than the intermediate concentration of the channel, so punch-through breakdown generally occurs in the middle of the channel.
(6) The poly gate length has an effect on the punch-through breakdown, and as the gate length increases, the breakdown increases. The impact of avalanche breakdown is also strictly speaking, but it is not so significant.
2) Drain-"Bulk Avalanche Breakdown:
This is simply a PN junction avalanche breakdown (**alanche Breakdown), mainly because the drain reverse bias voltage makes the PN junction depletion region broaden, then the reverse bias electric field is added to the PN junction reverse bias, making the electron accelerated impact The crystal lattice produces a new electron-hole pair, and then the electron continues to strike, so that the avalanche multiplies to cause breakdown, so the current of this breakdown increases almost rapidly, and the IV curve is almost vertical, which is very hard to burn. of. (This is not the same as the source-drain punch-through breakdown)
How to improve this juncTIon BV? Therefore, it is mainly from the characteristics of the PN junction itself, it is necessary to reduce the electric field in the depletion region, to prevent collisions from generating electron-hole pairs, and to reduce the voltage, it is impossible to increase the width of the depletion region, so it is necessary to change the doping profile. This is why the breakdown voltage of the abrupt junction (Abrupt juncTIon) is lower than that of the graded junction (Graded JuncTIon). This is what you have learned, and others are clouded.
Of course, in addition to the doping profile, there is a doping concentration. The larger the concentration, the narrower the width of the depletion region, so the stronger the electric field strength, the lower the breakdown voltage. There is also a rule that the breakdown voltage is usually more affected by the concentration of the lower concentration because the width of the depletion region is larger. The formula is BV=K*(1/Na+1/Nb). It can also be seen from the formula that if the Na and Nb concentrations are 10 times different, almost one of them can be ignored.
If the actual process finds that the BV is getting smaller and confirms that it is from the junction, then check your Source/Drain implant.
3) Drain-"Gate breakdown: This is mainly the gate oxide breakdown caused by Overlap between Drain and Gate. This is similar to GOX breakdown. Of course, it is more like Poly finger's GOX breakdown, so he May be more care poly profile and sidewall damage. Of course, this Overlap still has a problem with GIDL, which will also contribute Leakage to make BV lower.
The above is the three channels of MOSFET breakdown, usually the BV case is the first two.
The above is the breakdown under the Off-state, that is, when the Gate is 0V, but sometimes the Gate is turned on and the Drain is too high, which will cause breakdown. We call it On-state breakdown. This situation is particularly likely to occur when the Gate is at a lower voltage, or when the tube is just turned on, and is almost always an NMOS. So we usually test WVON with WAT,
Do not think it is very strange, but the test condition must pay attention to, Gate is not just adding voltage, it must be the voltage near Vt. (This article starts with the picture I posted, the lower the Vg, the on-state hits low)
It may be caused by Snap-back, but the test machine limitation cannot test the standard snap-back curve. In addition, it is also possible that the instantaneous current density is too large, causing a large amount of electrons to be accelerated by the electric field in the depletion region near the PN junction.
